1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a pillar type trench DRAM cell using a vertical MIS (Metal Insulator Semiconductor) as a transfer gate and the structure of a cell array of this DRAM cell.
2. Description of the Related Art
As the design rule decreases, the gate length of a MOS transistor (cell transistor) as a transfer gate of a DRAM cell must be decreased by the same length as the minimum design rule. Even when the gate length is thus decreased, the threshold value of the cell transistor must be held substantially constant when a leakage current while this transistor is OFF is taken into consideration.
To hold the threshold voltage of the cell transistor constant, the impurity concentration in a channel portion of the cell transistor must be increased by taking the short channel effect into account. However, increasing the impurity concentration in this channel portion increases the junction leakage current or deteriorates the pause characteristic.
As a countermeasure against this inconvenience, there is a method by which a cell transistor is changed from a conventional planar MOS transistor to a vertical MOS transistor, thereby releasing the gate length of this cell transistor from the limitations of a planar minimum design rule.
An example of the vertical transistor is “A Surrounding Gate Transistor (SGT) Cell for 64/256M bit DRAM” described in International Electron Device Meeting (IEDM) 1989 Technical Digest, pp. 23 to 26.
Unfortunately, in the structure of this conventional vertical transistor, a gate electrode is so formed as to surround the circumferential surface of a silicon pillar. This makes it difficult to reduce the pattern area when a DRAM cell array is designed. In addition, when the DRAM cell array is formed, alignment with peripheral transistors, which are transistors in a peripheral circuit, is difficult to obtain. So, it is difficult to simultaneously form the DRAM cell array and peripheral transistors.
Accordingly, it is being desired to realize a semiconductor memory by which the pattern area of a cell array of a pillar type trench DRAM cell using a vertical MOS transistor as a transfer gate is easily reduced, alignment with peripheral transistors is readily obtainable when this DRAM cell array is formed, and these DRAM cell array and peripheral transistors can be easily formed at the same time while an increase in the number of masks is minimized.